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| (R) SP508 Evaluation Board Manual FEATURES Easy Evaluation of SP508 Multi-Protocol Transceiver Eight (8) Drivers and Eight (8) Receivers Current Mode V.35 Drivers Internal Line or Digital Loopback Internal Transceiver Termination Resistors for V.11 and V.35 Termination Network Disable Option Fast 20Mbps Differential Transmission Rates Adheres to CTR1/CTR2 Compliancy Requirements PCB Friendly Flow-Through Pinout Improved ESD Tolerance for Analog I/Os Interface modes: RS-232 (V.28) EIA-530 (V.10&V.11) X.21 (V.11) EIA-530A (V.10&V.11) RS-449/V.36 (V.10&V.11) V.35 DESCRIPTION The SP508 Evaluation Board is designed to analyze the SP508 multi-protocol transceivers. The evaluation board provides access points to all of the driver and receiver I/O pins so that the user can measure electrical characteristics and waveforms of each signal. The SP508 Evaluation Board also includes a DB-25 serial port connector which is configured to a EIA-530 pinout. This allows easy connections to other DTE or DCE systems as well as network analyzers. The evaluation board also has dip switches to allow the user to select the mode of operation and test the data latch feature. The SP508 Evaluation Board Provides the means to test both local and remote driver/receiver Loopback as well as evaluate the SP508 in a DCE or DTE configuration. This Manual is split into sections to give the user the information necessary to perform a thorough evaluation of the SP508. The Board Layout section describes the I/O pins, the Dip switches and the other components used on the evaluation board. The board schematic, layout diagram, list of materials and DB-25 connector are also covered in the Board Layout section. The Using the SP508 Evaluation Board details the configuration of the SP508 evaluation board for parametric testing. rev. 7/7/03 SP508 Evaluation Board Manual (c) Copyright 2003 Sipex Corporation 1 1F VCC 10F 73 72 1F 1F 69 70 67 * Pins 1,26,45,64,71,77,80,84,88,93,98 = VCC ** Pins 2,25,44,52,68,74,82,86,91,96 = GND Pins 24 and 76 are no connects. VDD C1+ VCC* C1- C2+ C2VSS 66 1F 25-Pin D-Sub Connector Pins 2 14 24 11 Circuit # 103 113 113 105 108 109 140 141 Driver applies for DCE only on pins 5 and 12. Receiver applies for DTE only on Pins 5 and 12. Driver applies for DCE only on Pins 8 and 10. Receiver applies for DTE only on Pins 8 and 10. TxD 28 GND * * 97 100 92 95 87 90 83 85 75 78 81 79 65 SD(a) SD(b) TT(a) TT(b) ST(a) ST(b) RS(a) RS(b) TR(a) TR(b) RRC(a) RRC(b) RL(a) TxCE 29 ST 30 RTS 31 4 19 20 23 DTR 32 DCDDCE 33 RL 34 21 18 LL 35 63 LL(a) ON OFF Loopback No Loopback 105 115 114 106 107 109 125 142 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 RxD 36 48 SD(a) 47 SD(b) 50 TT(a) 49 TT(b) 53 ST(a) 51 ST(b) 55 RS(a) 54 RS(b) 57 TR(a) 3 16 17 9 15& 12& 5 13 6 22 8& 10& 22 25 1 0 1 0 Logic high Logic low RxC 37 TxC 38 CTS 39 DSR 40 56 TR(b) 60 RRC(a) 59 RRC(b) 61 RL(a) DCDDTE 41 RI 42 TM 43 62 LL(a) GND DECODER MODE D0 D1 D2 VCC 1 1 0 1 0 1 0 SDEN TTEN STEN RSEN TREN RRSEN RLEN LLEN RDEN RTEN TxCEN CSEN DMEN RRTEN ICEN TMEN D0 D1 D2 LOOPBACK 19 20 21 27 0 LATCH 23 TERM_OFF 22 1 VCC SHUTDOWN V.35 EIA-530 RS-232 EIA-530A RS-449 X.21 1 0 0 0 1 1 1 1 0 1 1 0 0 1 GND V35TGND1 V35TGND1 V35TGND1 V35TGND1 V35TGND1 99 94 89 46 58 1 1 1 1 1 2 2 2 2 2 GND Connect jumper to enable internal cable termination Figure 1 rev. 7/7/03 SP508 Evaluation Board Manual (c) Copyright 2003 Sipex Corporation 2 SP508 EVALUATION BOARD BOARD LAYOUT 1. The SP508 Evaluation board takes advantage of the products PCB friendly flow through pinout in its design as shown in Figure 1. 2. The SP508 Evaluation Board has been designed to easily and conveniently provide access to all inputs and outputs under test. 3. Figure 1 is a block diagram of the evaluation board showing the layout of the SP508 Evaluation Board. The block diagram shows the location of the driver and receiver access points as well as the DIP switches, VCC, GND and the DB-25 Connector. 4. I/O Pinouts The SP508 Evaluation Board has been designed to easily and conveniently provide access to all inputs and outputs to the device under test. Position the Board with the DB25 connector at the top and the Dip switches at the bottom. From this orientation , all driver inputs and outputs are on the righthand side and all receiver inputs and outputs are on the left-hand side eof the Board. 4.1. Each Driver has probe points for the input and outputs. There is a ground buss to the right of the drive outputs for the addition of loads to the driver outputs and to jumper the V.35 that is associated with the SD, TT, and ST driver. Each V.35 driver has a separate ground for the V.35 termination network internal to the device. 4.2. Each Receiver has probe points for the inputs and outputs. there is a ground buss to the left of the receiver outputs and a separate pin for the V.10 termination ground. 5. At the bottom of the board is a series of six(6) DIP switches. The DIP switch on the far left is for D_LATCH and TERM_OFF. Each driver and receiver has its own individual enable pin. The DIP switches to control the enable pins are located as the top center bank of switches for the driver and the middle center bank of switches for the receiver. The bottom center set of DIP switches is for the 3 bit decoder and the loopback control pin. The right hand DIP switches allow the user to tie the ST driver outputs to the TxC receiver inputs and the RRC driver outputs to the RRT receiver inputs. 6. Also located on the SP508 evaluation board are the four 10uf charge pump capacitors, a 10uf bypass capacitor for VCC and a 50 termination resistor. 7. Table 1 shows the pinout of the DB-25 connector used to connect to a communication analyzer such as the TTC Firebird 6000. 1 13 14 25 Figure 2: RS-232 & EIA530 Connector (ISO 2110), DTE Connector DB-25 Male, DCE Connector DB25 Female rev. 7/7/03 SP508 Evaluation Board Manual (c) Copyright 2003 Sipex Corporation 3 Table 1. EIA-232 Signal Name source Mnemonic Pin EIA-530 Mnemonic Pin EIA-449 Mnemonic Pin V.35 Mnemonic Pin X.21 Mnemonic Pin Shield Transmitted data -- DTE -- BA 1 2 -- BA(A) BA(B) 1 2 14 3 16 4 19 5 13 6 22 20 23 7 8 10 15 12 17 9 18 21 -- 24 11 25 -- SD(A) SD(B) RD(A) RD(B) RS(A) RS(B) CS(A) CS(B) DM(A) DM(B) TR(A) TR(B) SG RR(A) RR(B) ST(A) ST(B) RT(A) RT(B) LL RL -- TT(A) TT(B) TM 1 4 22 6 24 7 25 9 27 11 29 12 30 19 13 31 5 23 8 26 10 14 -- 17 35 18 -- 103 103 104 104 105 A P S R T C -- Circuit T(A) Circuit T(B) Circuit R(A) Circuit R(B) Circuit C(A) Circuit C(B) 1 2 9 4 11 3 10 5 12 Received Data DCE BB 3 BB(A) BB(B) Request To Send DTE CA 4 CA(A) CA(B) Clear To Send DCE CB 5 CB(A) CB(B) 106 D Circuit I(A) Circuit I(B) DCE Ready (DSR) DCE CC 6 CC(A) CC(B) 107 E DTE Ready (DTR) DTE CD 20 CD(A) CD(B) 108 H* Signal Ground Recv. Line Sig. Det. (DCD) Trans. Sig. Elemt. Timing Recv. Sig. Elemt. Timing Local Loopback Remote Loopback Ring Indicator Trans. Sig. Elemt. Timing Test Mode -- DCE AB CF 7 8 AB CF(A) CF(B) 102 109 B F Circuit G 8 DCE DB 15 DB(A) DB(B) 114 114 115 115 141 140 125 113 113 142 Y AA V X L* N* J* U* W* NN* Circuit S(A) Circuit S(B) Circuit B(A)** Circuit B(B)** 6 13 7 14 DTE RL 17 DD(A) DD(B) DCE DTE DCE DTE DD LL CE DA 18 21 22 24 LL RL -- DA(A) DA(B) Circuit X(A)** Circuit X(B)** 7 14 DCE TM 25 TM * Optional signals ** Only one of the two x.21 signals, Circuit B or X, can be implemented and active at one time. rev. 7/7/03 SP508 Evaluation Board Manual (c) Copyright 2003 Sipex Corporation 4 Table 2 Driver Output Pin MODE (D0,D1,D2) T1OUT(a) T1OUT(b) T2OUT(a) T2OUT(b) T3OUT(a) T3OUT(b) T4OUT(a) T4OUT(b) T5OUT(a) T5OUT(b) T6OUT(a) T6OUT(b) T7OUT(a) T8OUT(a) V.35 Mode 001 V.35 V.35 V.35 V.35 V.35 V.35 V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 EIA-530 Mode 010 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 RS-232 EIA-530A RS-449 X.21 Mode (V.28) Mode Mode (v.36) Mode (v.11) 011 V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 100 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 V.11 V.11 V.10 V.10 101 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 110 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 High-Z High-Z Shutdown 111 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z TxD(a) TxD(b) TxCE(a) TxCE(b) TxC_DCE(a) TxC_DCE(b) RTS(a) RTS(b) DTR(a) DTR(b) DCD_DCE(a) DCD_DCE(b) RL LL Suggested Signal TABLE 3 Receiver Input Pin MODE (D0,D1,D2) R1IN(a) R1IN(b) R2IN(a) R2IN(b) R3IN(a) R3IN(b) R4IN(a) R4IN(b) R5IN(a) R5IN(b) R6IN(a) R6IN(b) R7IN(a) R8IN(a) V.35 Mode 001 V.35 V.35 V.35 V.35 V.35 V.35 V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 EIA-530 Mode 010 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 RS-232 EIA-530A RS-449 X.21 Mode (V.28) Mode mode (v.36) Mode (v.11) 011 V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 100 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 V.11 V.11 V.10 V.10 101 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 110 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 High-Z High-Z Shutdown 111 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z RxD(a) RxD(b) RxC(a) RxC(b) TxC_DTE(a) TxC_DTE(b) CTS(a) CTS(b) DSR(a) DSR(b) DCD_DTE(a) DCD_DTE(b) RI TM Suggested Signal rev. 7/7/03 SP508 Evaluation Board Manual (c) Copyright 2003 Sipex Corporation 5 USING THE EVALUATION BOARD Recommended Equipment * Oscilloscope * Digital multimeter * Signal Generator capable of >40MHz * Communications Analyzer (such as Firebird 6000) Parametric Evaluation Located on the board are two pins identified as VCC and SIGNAL GND. Connect VCC to a +5V DC supply. If possible limit the supply current to 0.5 to 1.0 Amps. Be sure to have power off when connecting the supply to the board. SP508 Decoder The SP508 uses a 3 bit decoder to designate the protocol selected. There is also a decoder latch pin available. Table 2 and Table 3 show the decoder modes for the driver and receiver. Upon power up the latch pin needs to be in a transparent state (logic low or floating) or the SP508 will be in an unknown state. Note that D0, D1, and D2 set as logic high will put the device shutdown overriding all individual enable/disable lines and the drivers outputs and receiver inputs will tri-state. In shutdown mode the termination resistors also disconnect. Driver Evaluation Each driver has an internal pull-up so that it is in a defined state when the input is open. Connect a system clock or a signal generator with a TTL-level output and the appropriate frequency within the acceptable range of the driver under test to driver input you wish to evaluate. There is an individual enable line for each driver that can be used to tri-state the driver. Each enable line has an internal pull up or pull down insure the driver is enabled if the enable pin is not connected or floating. Set the appropriate DIP switch to the "OFF" position to enable the driver under test. Once the power is on and the driver input receives a signal, the driver outputs can be analyzed with an oscilloscope or a digital multimeter. Mode selection can be performed at any time by changing the state of the DIP switches for the 3 bit decoder. The appropriate termination for the driver under test can be added to driver output and tied to the ground buss. Receiver Evaluation The SP508 receivers have internal termination appropriate for V.35 and RS-422 modes (refer to the SP508 data sheet for more detail on the receiver termination). The is activated when the receiver is set to act as a V.11 receiver (see Table 3) and the TERM_OFF pin is logic "0". Each receiver has a fail-safe feature than outputs a logic "1" when the receiver in open, terminated but open, or shorted together. There is an individual enable line for each receiver that can be used to tri-state the driver. Each enable line has an internal pull up or pull down to insure the receiver is enabled if the enable pin is not connected or floating. Set the appropriate DIP switch to the "OFF" position to enable the receiver under test. As with the drivers the mode selection can be performed at any time after power up by changing the state of the 3 bit decoder. To evaluate the receiver the appropriate input signal needs to be applied. To accomplish this provide a signal from an external source or use the SP508 driver output and jumper it to the receiver input. For single ended receivers tie the active driver output to the active receiver input. For differential drivers tie the "A" driver output to the "A" receiver input and the "B" driver output to the "B" receiver input. Using the TTL signal on the driver input will allow the analysis receiver levels and timing characteristics. The DIP switches on the right hand side also provide a means of evaluating the TxC and RRT receivers by tying the ST and RRC drivers to the appropriate receivers eliminating the need for jumper wires. rev. 7/7/03 SP508 Evaluation Board Manual (c) Copyright 2003 Sipex Corporation 6 USING THE EVALUATION BOARD: continued Driver Receiver Remote Loopback. The following example uses the ST driver looped back into the TxC receiver, using the 3 bit decoder configure the SP508 for the desired protocol. Connect a jumper cable between the ST(a) pin and the TxC(a) pin. If your mode select is for a differential driver/ receiver, then also connect a jumper cable between the ST(b) pin and the TxC(b) pin. next connect a signal generator to the ST input pin. The signal generator output must be a TTL-level output at a frequency within the acceptable range of the driver mode under test. Be sure that the STEN and the TxCEN DIP switches are set to enable the ST driver and TxC receiver and that the DIP switches tying the ST driver to the TxC receiver are off (refer to section 5.0 Dip switch guide). The driver outputs are now connected back to the receiver inputs so that the driver input to receiver output can be examined. This configuration is similar for the other drivers. Driver Receiver Local Loopback The SP508 has the ability to provide an internal loopback. This feature is invoked by a logic "0" on the LOOPBACK pin. The driver input and receiver output characteristics adhere to the appropriate specifications outlined in the data sheet under loopback conditions. The LOOPBACK pin has in internal pull-up resistor so that the SP508 defaults to normal operation during powerup or if the pin is left floating. DCE DTE selectable configuration * Configure the decoder for the desired mode. * The SP508 evaluation board has dip switches setup to allow for the evaluation of a selectable DCE DTE configuration. * Switch the STEN and RRCEN to the ON position. This will disable the ST and RRC driver outputs. (Refer to the DIP switch guide on Page 8) * Switch the rev. 7/7/03 SP508 Evaluation Board Manual (c) Copyright 2003 Sipex Corporation 7 DIP SWITCH USERS GUIDE Driver Enable Dip Switch (off = logic 1, on = logic 0) The individual switches in the off position leaves the individual enable pin floating (internally pulled up or down?) which enables the driver. The switch in the on position ties the high true enable pins to ground and the low true enable pin (LLEN) to VCC thereby disabling the individual drivers. Receiver Enable Dip Switch (off = logic 0, on = logic 1) The individual switches in the off position leaves the individual enable pins floating (internally pulled down or up?) which enables the receiver. The switch in the on position ties all of the enable pins to VCC even the high true TMEN. The TMEN pin is always high no matter what position the dip switch is in. To disable the TM receiver the SP508 DIP SWITCH TRUTH TABLE Switch D0 D1 D2 LOOPBACK TERM_OFF D_LATCH SDEN TTEN STEN RSEN TREN RRCEN RLEN LLEN RDEN RTEN TXCEN CSEN DMEN RRTEN ICEN TMEN rev. 7/7/03 DIP switch must be off and the external pin labeled TMEN is to be jumped to ground. Decoder DIP Switch (off = logic 1, on = logic 0) The decoder DIP switch is configured such that the switch in the off position allows the decoder pins to float as well as the notLOOPBACK pin. (all of these pins are assumed to have internal pull-ups.) The dip switch in the on position grounds each of these pins. DCE_DTE Selectable Switches * Switch bank 1 ON = ST driver outputs tied to TxC receiver inputs and also tied to DSUB connector for remote evaluation. * Switch bank 2 ON = RRC driver outputs tied to RRT receiver inputs and also tied to D-SUB connector for remote evaluation. ON LOGIC 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 OFF LOGIC 1 1 1 1 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 DECODER DECODER DECODER Logic 0 indicates SP508 is in LOOPBACK mode Logic 1 internal termination is disables Logic 0 Latch is disabled Logic 1 TXD driver is enabled Logic 1 TXCE driver is enabled Logic 1 ST driver is enabled Logic 1 RTS driver is enabled Logic 1 DTR driver is enabled Logic 1 DCD_DCE driver is enabled Logic 1 SD driver is enabled Logic 0 LL driver is enabled Logic 0 RXD receiver is enabled Logic 0 RXT receiver is enabled Logic 0 TXC receiver is enabled Logic 0 CTS receiver is enabled Logic 0 DSR receiver is enabled Logic 0 DCD_DTE receiver is enabled Logic 0 RI receiver is enabled Logic 1 TM receiver is enabled (c) Copyright 2003 Sipex Corporation SP508 Evaluation Board Manual 8 SP508 PIN ASSIGNMENTS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol VCC GND SDEN TTEN STEN RSEN TREN RRCEN RLEN LLEN* RDEN* RTEN* TxCEN* CSEN* DMEN* RRTEN* ICEN* TMEN D0 D1 D2 TERM_OFF D_LATCH* N/C GND VCC LOOPBACK* TXD TxCE ST DTR RTS DCD_DCE RL LL RXD RXC TXC CTS DSR DCD_DTE RI TM GND VCC V35RGND RD(b) RD(a) RT(b) RT(a) Description +5V Power Supply Input Signal Ground TxD Driver Enable input TXCE Driver Enable Input ST Driver Enable Input RTS Driver Enable Input DTR Driver Enable Input DCDDCE Driver Enable Input RL Driver Enable Input LL Driver Enable Input RxD Receiver Enable Input RxT Receiver Enable Input TxC Receiver Enable Input CTS Receiver Enable Input DSR Receiver Enable Input DCDDTE Receiver Enable Input RI Receiver Enable Input TM Receiver Enable Input Mode Select Input Mode Select Input Mode Select Input Termination Disable Input Decoder Latch Input No Connection Signal Ground +5V Power Supply Input Loopback Mode Enable Input TXD Driver TTL Input TXCE Driver TTL Input ST Driver TTL Input RTS Driver TTL Input DTR Driver TTL Input DCDDCE Driver TTL Input RL Driver TTL Input LL Driver TTL Input RXD Receiver TTL Output RXC Receiver TTL Output TXC Receiver TL Output CTS Receiver TTL Output DSR Receiver TTL Output DCDDTE Receiver TTL Output RI Receiver TTL Output TM Receiver TTL Output Signal Ground +5V Power Supply Input Receiver Termination Reference RXD Non-inverting Input RXD Inverting Input RXT Non-Inverting Input RXT Inverting Input PIN 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol TXC(b) GND TXC(a) CS(b) CS(a) DM(b) DM(a) V10GND RRT(b) RRT(a) IC(a) TM(a) LL(a) VCC RL(a) Vss C2GND C1C2+ VCC C1+ Vdd GND TR(a) N/C VCC TR(b) RRC(b) VCC RRC(a) GND RS(a) VCC RS(b) GND ST(a) VCC V35TGND3 ST(b) GND TT(a) VCC V35TGND2 TT(b) GND SD(a) VCC V35TGND1 SD(b) Description TXC Non-Inverting Input Signal Ground TXC Inverting Input CTS Non-Inverting Input CTS Inverting Input DSR Non-Inverting Input DSR Inverting Input V.10 Rx Reference Node DCDDTE Non-Inverting Input DCDDTE Inverting Input RI Receiver Input TM Receiver Input LL Driver Output +5V Power Supply Input' RL Driver Output -2xVCC Charge pump Output Charge pump Capacitor Signal Ground Charge pump Capacitor Charge pump Capacitor +5V Power Supply Input Charge pump Capacitor 2xVxx Charge Pump Output Signal Ground DTR Inverting Output No Connection +5V Power Supply Input DTR Non-Inverting Output DCDDCE Non-Inverting Output +5V Power Supply Input DCDDCE Inverting Output Signal Ground RTS Inverting Output +5V Power Supply Input RTS Non-Inverting Output Signal Ground ST Inverting Output +5V Power Supply Input ST Termination Reference ST Non-Inverting Output Signal Ground TXCE Inverting Output +5V Power Supply Input TXCE Termination Reference TXCE Non-Inverting Output Signal Ground TXD Inverting Output +5V Power Supply Input TXD Termination Reference TXD Non-Inverting Output Note:N/C Pins should be left floating as internal signals may be present. Ensure all VCC and ground connections are made before operating device. rev. 7/7/03 SP508 Evaluation Board Manual (c) Copyright 2003 Sipex Corporation 9 ORDERING INFORMATION Model Package SP508CF ........................................................................................................................ 100-pin JEDEC LQFP SP508CB ....................................................................................................................................... 132-pin BGA SP508CEB ................................................................................................................. SP508 Evaluation Board Corporation SIGNAL PROCESSING EXCELLENCE Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. rev. 7/7/03 SP508 Evaluation Board Manual (c) Copyright 2003 Sipex Corporation 10 |
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